1) Field of the Invention
The present invention is related to a fractional-frequency-modulation phase-locked-loop (PLL) synthesizer that suppresses spurious elements.
2) Description of the Related Art
A fractional-frequency-modulation PLL synthesizer allows fractional (sub-decimal point) frequency modulation settings as an average frequency modulation by periodically switching frequency modulation of variable frequency divider. The fractional-frequency-modulation-type PLL synthesizer has two prominent merits as explained below:
(1) It is possible to reduce frequency modulation by a variable frequency divider owing to a higher reference frequency (phase comparator frequency) setting than that of channel resolution. This leads to an increase in PLL loop gain, enabling a reduction in frequency switching time.
(2) It is possible to reduce in-phase noise due to the reduction of frequency modulation of the variable frequency divider.
FIG. 3 shows the basic configuration of a conventional fractional-frequency-modulation PLL synthesizer. In this diagram, reference numeral 1 represents a reference oscillator, 2 a reference frequency divider, 3 a phase comparator, 4a a charge pump circuit, 5 a loop filter, 6 a voltage control oscillator, 7 a variable frequency divider, 8 a frequency changing circuit, 9 a shift resistor, 10 an adder, 11 an accumulator and 13a a charge pump bias circuit.
The operation of the conventional fractional-frequency-modulation PLL synthesizer is explained with the help of FIG. 3 and FIG. 4. As shown in FIG. 3, the reference oscillator 1 generates a signal Fosc and supplies the generated signal to the reference frequency divider 2. The reference frequency divider 2 divides the signal Fosc to obtain a reference frequency signal Fref. The reference frequency divider 2 feeds the reference frequency signal Fref to the phase comparator 3. The phase comparator 3 compares a signal received from the variable frequency divider 7 with the reference frequency signal Fref and generates an UP or a DOWN signal based on the comparison and sends the UP or the DOWN signal to the charge pump circuit 4a. The charge pump circuit 4a outputs a current value to the loop filter 5. The loop filter 5 converts the current value into a voltage value and supplies the voltage value to the voltage control oscillator 6. The voltage control oscillator 6 generates a signal Fvco from the received voltage value and supplies the signal Fvco into the variable frequency divider 7. Thus, a PLL is formed.
In the case of an integer (whole number) frequency PLL, the integer frequency is directly supplied to variable frequency divider 7. In the case of a fractional frequency PLL, however, the shift register 9 gets connected, forming frequency changing circuit 8 and enables equivalent fractional frequency modulation through periodic supply of N or N+1 frequency to the variable frequency divider 7. In the shift register 9, the value of frequency modulation of the variable frequency divider 7 is set beforehand. Integer frequency values are sent to the adder 10 in the frequency switching circuit while fractional frequency values are sent to the accumulator 11. To be precise, the frequency switching circuit 8 changes the frequency to N+1 only m out of 2k times of reference frequency Fref signal pulses. For the rest 2k-m times, the frequency is changed to N, thereby enabling an average setting of frequency modulation equivalent to (N+m)/2k.
As an example, FIG. 4 shows the relationship between the reference frequency Fref, output of the variable frequency divider 7, and the phase error output signal when m=1 and K=2, i.e., when modulation is (N+1)/4. In this example, of 4 outputs of the variable frequency divider 7, only 3 outputs are divided by N while for the remaining output is divided by N+1. The average frequency for 4 outputs is (N+1)/4. Due to generation of phase error with reference frequency Fref, the amount of phase error (in this case phase advancement) is sent to the phase comparator 3 in the form of a signal. Since the cycle of this signal is 4 times that of the reference frequency Fref, a spurious frequency equivalent to xc2xc th of the reference frequency is generated.
Owing this, conventionally, the charge pump bias circuit 13a is provided as shown in FIG. 5. This charge pump bias circuit 13a takes the output of the accumulator 11 as its input and delivers its output to the charge pump circuit 4a. The charge pump bias circuit 13a takes ICPMBIAS as standard bias current and is constituted of K units of current Miller circuits in which transistor size is changed so as to make the Miller current 1:21:22: . . . :2kxe2x88x921. N channel MOS transistor drain serves as a commonly connected output to the charge pump bias circuit 13a and it is also connected to P channel MOS transistor drain which serves as a standard bias current source for charge pump circuit 4a. Further, the output of the accumulator 11 (K bit in the case of FIG. 5) is connected to N channel MOS transistor gate in such a way that lower bits are connected to lower Miller ratio circuits and higher bits are connected to higher Miller ratio circuits.
The charge pump bias circuit 13a thus formed generates an output proportionate to the signal input from the accumulator 11 which exclusively gets added to the source current of charge pump circuit 4a. 
The charge pump circuit 4a, on the other hand, takes ICPBIAS as a reference bias current and multiplies the current value by N times according to the Miller ratio of the current Miller circuit. An arrangement is made in such a way that a source current is sent out from PMOS transistor in accordance with UP signal from phase comparator 3 while sync-current flows from NMOS transistor in accordance with DOWN signal from phase comparator 3.
As a result of this arrangement, the phase error of fractional-frequency-modulation PLL used to be cancelled by the addition of phase error compensation current (spurious cancel current) proportional to the value of the output signal of accumulator 11 used in fractional frequency modulation to the source current of the charge pump circuit 4a. 
According to the conventional art, the time for which phase error compensation current addition takes place is equivalent to gate delay generated due to a dead band of the phase comparator 3 as shown in FIG. 6. That is, it is the time for which a charge pump current sync-source is switched on simultaneously.
However, the gate delay time of the phase comparator 3 varies with manufacturing variation in the elements, operating temperature and operating source voltage etc. This in effect leads to variation in the amount of spurious signal suppression. Especially, in the case of application in wireless equipments like cellular/mobile phones, the spurious signal works as an interference and creates problems.
As a result, conventionally, as shown in FIG. 7, a separate ring oscillator circuit having the same elements as the delay gate is provided to suppress fluctuation in the amount/degree of suppression of a spurious signal. The oscillation cycle of this ring oscillator circuit is monitored to generate a spurious cancel current proportional to the oscillation cycle as a bias source has been also provided.
However, even in such cases, it is not possible to eliminate variation between gate elements resulting from reasons like manufacturing variation etc. Moreover, when the amount of variation is large, the degree of spurious signal suppression gets deteriorates and poses an operational problem that needs to be solved.
It is an object of this invention to provide a fractional-frequency-modulation-type PLL synthesizer that suppresses the spurious signal despite presence of the manufacturing variation in the gate elements.
The fractional-frequency-modulation-type PLL synthesizer according to the present invention includes a phase comparator. The phase comparator includes a gate delay element that operates as a ring oscillator when locking a specific frequency. Moreover, the gate delay element prevents a dead band in the event of fractional frequency operation.
These and other objects, features and advantages of the present invention are specifically set forth in or will become apparent from the following detailed descriptions of the invention when read in conjunction with the accompanying drawings.